Processor-based systems, such as computer systems, use memory devices, such as dynamic random access memory (“DRAM”) devices, to store instructions and data that are accessed by a processor. These memory devices are typically used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory. In response to the commands and addresses, data is transferred between the system memory and the processor. The memory controller is often part of a system controller, which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a PCI bus.
Although the operating speed of memory devices has continuously increased, this increase in operating speed has not kept pace with increases in the operating speed of processors. Even slower has been the increase in operating speed of memory controllers coupling processors to memory devices. The relatively slow speed of memory controllers and memory devices limits the data bandwidth between the processor and the memory devices.
In addition to the limited bandwidth between processors and memory devices, the performance of computer systems is also limited by latency problems that increase the time required to read data from system memory devices. More specifically, when a memory device read command is coupled to a system memory device, such as a synchronous DRAM (“SDRAM”) device, the read data are output from the SDRAM device only after a delay of several clock periods. Therefore, although SDRAM devices can synchronously output burst data at a high data rate, the delay in initially providing the data can significantly slow the operating speed of a computer system using such SDRAM devices.
One approach to alleviating the memory latency problem is to use multiple memory devices coupled to the processor through a memory hub. In a memory hub architecture, a system controller or memory hub controller is coupled to several memory modules, each of which includes a memory hub coupled to several memory devices. The memory hub efficiently routes memory requests and responses between the controller and the memory devices. Computer systems employing this architecture can have a higher bandwidth because a processor can access one memory module while another memory module is responding to a prior memory access. For example, the processor can output write data to one of the memory modules in the system while another memory module in the system is preparing to provide read data to the processor. The operating efficiency of computer systems using a memory hub architecture can make it more practical to vastly increase data bandwidth of a memory system. A memory hub architecture can also provide greatly increased memory capacity in computer systems.
Although there are advantages to utilizing a memory hub for accessing memory devices, the design of the hub memory system, and more generally, computer systems including such a memory hub architecture, becomes increasingly difficult. For example, in many hub based memory systems, the processor is coupled to the memory via a high speed bus or link over which signals, such as command, address, or data signals, are transferred at a very high rate. However, as transfer rates increase, the time for which a signal represents valid information is decreasing. As commonly referenced by those ordinarily skilled in the art, the window or “eye” for when the signals are valid decreases at higher transfer rates. With specific reference to data signals, the “data eye” decreases. As understood by one skilled in the art, the data eye for each of the data signals defines the actual duration that each signal is valid after various factors affecting the signal are considered, such as timing skew, voltage and current drive capability, and the like. In the case of timing skew of signals, it often arises from a variety of timing errors such as loading on the lines of the bus and the physical lengths of such lines.
As data eyes of the signals decrease at higher transfer rates, it is possible that one or more of a group of signals provided in parallel will have arrival times such that not all signals are simultaneously valid at a receiving entity, and thus cannot be successfully captured that entity. For example, where a plurality of signals are provided in parallel over a bus, the data eye of one or more of the particular signals do not overlap with the data eyes of the other signals. In this situation, the signals having non-overlapping data eyes are not valid at the same time as the rest of the signals, and consequently, cannot be successfully captured by the receiving entity.
Clearly, as those ordinarily skilled in the art will recognize, the previously described situation is unacceptable. As it is further recognized by those familiar in the art of high speed digital systems, signal timing is an issue that has become increasingly more significant in the design of systems capable of transferring and transmitting information at high speeds because signal timing can be affected by many things. As a result, testing memory devices that are subject to variations in the timing relationships between signals, whether command, address, or data signals, is becoming a more critical step in the production of memory devices that are to be used in a high-speed digital system.
Production testing is typically accomplished using sophisticated testing equipment that is coupled to several memory devices to simultaneously test the devices. During testing, the testing equipment couples signals to and from integrated circuit nodes sometimes using a test probe that makes electrical contact with the circuit nodes. However, such probes can introduce loading effects that change the characteristic of the signals being evaluated. Although probes are specifically designed to have high impedance and low capacitance to minimize loading issues and the introduction of noise, there is still in many cases, an unacceptable level of loading that changes the character of a signal to such a degree that it cannot be accurately evaluated. Also, the propagation delays in coupling signals between the integrated circuit nodes and the test equipment may introduce delays that make it impossible to accurately determine timing relationships within the integrated circuit. For example, the testing equipment may apply memory command and address signals to the memory device with a specific range of timing relationships to write data signals that are also applied to the memory device. If the memory device is able to properly read the write data, the assumption is made that the memory device is able to operate within this range of timing relationships. However, there can be no assurance that the command and address signals and the write data signals are actually coupled to circuit nodes in the memory device with this same range of timing relationships. Therefore, the memory device may not actually function properly with the timing relationships that were used during the testing.
The difficulty in accurately controlling and/or determining the actual timing relationships between signals applied to or internal to memory devices is exacerbated when the memory devices are accessible only through interface circuitry. For example, where several memory devices are coupled to a memory hub, the memory devices are accessible only through the memory hub. Although production testing equipment may be able to accurately control and determine the timing relationships between signals applied to the interface circuitry, such equipment cannot control or determine the timing relationships of the signals in the memory devices after the devices have been packaged with the interface circuitry so that the signals coupled to and from the memory devices must be coupled through the interface circuitry.
Another problem that can be encountered in testing high-speed memory devices using conventional production testing equipment is associated with obtaining control over the memory bus in order to perform evaluation. Again, this problem is exacerbated when memory devices are accessible to production testing equipment only through interface circuitry, such as a memory hub. The ability to evaluate a memory system often requires that specific signals of interest can be captured and analyzed by obtaining control of the memory bus and monitoring the interaction of the signal with the bus itself. Unless control over the memory bus can be obtained, analysis becomes a difficult task. However, obtaining control over the memory bus is a difficult task in itself because conventional approaches often interfere with the normal operation of the computer system, thus, preventing accurate analysis of the memory system under true, normal operating conditions.
There is therefore a need for a system and method that allows memory devices to be tested through interface circuitry in a manner that does not affect the normal operation of the memory device and that provides accurate control and determination of timing relationships between signals applied to or received from the memory device. In particularly, there is a need for a system and method that allows the timing relationships between signals applied to or received from memory devices to be controlled and determined even though the memory devices are contained in a memory hub module.